8 Bit Array Multiplier Verilog Code < 95% Updated >

assign final_sum[7] = final_carry[6];

—Array multiplier, Verilog, digital design, parallel multiplication, full adder. 8 bit array multiplier verilog code

// Generate partial products: pp[i][j] = A[i] & B[j] genvar i, j; generate for (i = 0; i < 8; i = i + 1) begin : pp_gen for (j = 0; j < 8; j = j + 1) begin : bit_gen assign pp[i][j] = A[i] & B[j]; end end endgenerate assign final_sum[7] = final_carry[6]

integer i, j; initial begin $monitor("Time=%0t | A=%d B=%d | Product=%d (expected %d)", $time, A, B, P, A*B); for (i = 0; i < 256; i = i + 1) begin for (j = 0; j < 256; j = j + 1) begin A = i; B = j; #10; if (P !== A*B) begin $display("ERROR: %d * %d = %d, but got %d", A, B, A*B, P); $finish; end end end $display("All tests passed."); $finish; end endmodule Running the testbench yields correct multiplication for all 65,536 input combinations. Example: generate for (i = 0

// Row 7: full adders for all but last column generate for (j = 0; j < 7; j = j + 1) begin : final_row if (j == 0) begin ha final_ha ( .a (pp[7][0]), .b (sum[6][j]), .sum (final_sum[j]), .carry(final_carry[j]) ); end else begin fa final_fa ( .a (pp[7][j]), .b (sum[6][j-1]), .cin (final_carry[j-1]), .sum (final_sum[j]), .cout (final_carry[j]) ); end end endgenerate

// First row (i=0) assign s[0][0] = pp[0][0]; assign c[0][0] = 1'b0; genvar j; generate for (j = 1; j < 8; j = j + 1) begin assign s[0][j] = pp[0][j]; assign c[0][j] = 1'b0; end endgenerate

// Assign product bits assign P[1] = sum[0][0]; assign P[2] = sum[1][1]; assign P[3] = sum[2][2]; assign P[4] = sum[3][3]; assign P[5] = sum[4][4]; assign P[6] = sum[5][5]; assign P[7] = sum[6][6]; assign P[8] = final_sum[0]; assign P[9] = final_sum[1]; assign P[10] = final_sum[2]; assign P[11] = final_sum[3]; assign P[12] = final_sum[4]; assign P[13] = final_sum[5]; assign P[14] = final_sum[6]; assign P[15] = final_sum[7];